1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a multilayer interconnection technique.
2. Description of the Background Art
In recent years, a wiring has become finer and more multilayered with an enhancement in the integration and function of a semiconductor device. In a method of manufacturing the semiconductor device, a multilayer interconnection technique has been one of important techniques.
FIG. 17 is a longitudinal sectional view illustrating a conventional semiconductor device 101P having a two-layer interconnection structure. The semiconductor device 101P comprises a silicon substrate 1P. In FIG. 17, various elements formed on a surface of the silicon substrate 1P are omitted.
An interlayer insulating film 2P composed of a silicon oxide (SiO2) is formed on the silicon substrate 1P. The interlayer insulating film 2P is provided with a contact hole 2HP in a direction of a thickness thereof and a hole 2MP for a mark such as an alignment mark. In a semiconductor device having a minimum line width of 0.25 xcexcm, that is, a so-called quarter micron generation semiconductor device, generally, in the case in which the semiconductor device 101P is seen from an upper surface, the contact hole 2HP and a via hole 4HP which will be described below have dimensions of approximately 0.3 to 0.4 xcexcm and the hole 2MP for a mark has a dimension of approximately 1 to 10 xcexcm.
A metal layer 7HP forming a so-called plug is buried in the contact hole 2HP. The xe2x80x9cplugxe2x80x9d means a conductive layer for electrically connecting conductive layers such as wirings provided with an interlayer insulating film interposed therebetween. On the other hand, a metal layer 7MP having the shape of a so-called side-wall spacer is formed on a side wall of the hole 2MP for a mark. The metal layer 7MP is formed of the same material as the material of the metal layer 7HP.
Furthermore, a metal layer 3HP constituting a wiring or a wiring layer is formed on the interlayer insulating film 2P in contact with the plug 7HP. On the other hand, a metal layer 3MP is formed to cover the hole 2MP for a mark.
An interlayer insulating film 4P composed of a silicon oxide is formed to cover the wiring 3HP, the metal layer 3MP and the interlayer insulating film 2P. The interlayer insulating film 4P has a thickness of approximately 700 to 1000 nm (7000 to 10000 angstrom), for example. The interlayer insulating film 4P has a contact hole or a via hole 4HP reaching the wiring 3HP and the via hole 4HP is filled with a plug 8HP. A wiring 6HP is formed on the interlayer insulating film 4P in contact with the plug 8HP. On the other hand, a concave portion 4MP is formed above the hole 2MP for a mark on the surface 4SP side of the interlayer insulating film 4P which is opposite to the substrate 1.
In FIG. 17, a region HP including the plugs 7HP and 8HP, the wirings 3HP and 6HP and the like is equivalent to an element region or an element formation region where various elements (not shown) of the semiconductor device 101P are formed. On the contrary, a region MP including the hole 2MP for a mark is equivalent to a region where an auxiliary pattern such as an alignment mark to be used in a manufacturing process is formed.
Next, a method of manufacturing the conventional semiconductor device 101P will be described below with reference to each of longitudinal sectional views of FIGS. 18 to 20 in addition to FIG. 17.
First of all, a silicon oxide (plasma oxide) is deposited, by a plasma CVD (Chemical Vapor Deposition) method, on a silicon substrate 1P where the above-mentioned various elements are formed. The silicon oxide is flattened by using an etch-back method or a CMP (Chemical Mechanical Polishing) method, thereby forming an interlayer insulating film 2P.
Next, the interlayer insulating film 2P is wholly coated with a resist (not shown). The resist is patterned to have such a pattern as to correspond to a contact hole 2HP, a hole 2MP for a mark and the like by a photolithographic technique. By a RIE (Reactive Ion Etching) method using the patterned resist as a mask, the interlayer insulating film 2P is opened to form the contact hole 2HP and the hole 2MP for a mark. Then, the resist is removed by an oxygen plasma or the like.
Subsequently, a predetermined metal material is deposited by a sputtering method, for example, to cover the whole interlayer insulating film 2P. Then, the metal layer is etched back to form a plug 7HP. At this time, the dimension of the hole 2MP for a mark is greater than that of the contact hole 7HP as described above. In the hole 2MP for a mark, therefore, the metal layer remains in the form of a side-wall spacer, thereby constituting a metal layer 7MP.
Then, a predetermined metal material is deposited to cover the whole interlayer insulating film 2HP. Thereafter, the whole metal layer is coated with a resist (not shown). The resist is patterned to have such a pattern as to correspond to a wiring 3HP and a metal layer 3MP by a photolithographic technique. Then, the metal layer is patterned to form the wring 3HP and the metal layer 3MP by a RIE method using the patterned resist as a mask. Subsequently, the resist is removed by the oxygen plasma or the like. By the above-mentioned steps, a semiconductor device in the state shown in FIG. 18 is obtained.
As shown in FIG. 19, then, a silicon oxide film 4AP having a thickness of approximately 1500 to 2500 nm (15000 to 25000 angstrom), for example, is formed by using a plasma CVD method to wholly cover the interlayer insulating film 2P, the wiring 3HP and the metal layer 3MP.
The silicon oxide film 4AP is formed to have a concave portion 4MAP corresponding to the concave shape of the hole 2MP for a mark above the hole 2MP for a mark. Such a concave portion 4MAP is easily formed above the comparatively large hole 2MP for a mark as in the case in which the hole 2MP for a mark in a plane view of the silicon substrate 1P has a dimension of approximately 1 xcexcm or more, for example. Moreover, in the case in which the hole 2MP for a mark has such a depth as to exceed 1.5 xcexcm, for example, the concave portion is easily formed deeply.
Next, the silicon oxide film 4AP is polished and flattened by using the CMP method to form an interlayer insulating film 4P shown in FIG. 20. In this case, the silicon oxide film provided on the wiring 3HP is polished to have a thickness of approximately 700 to 1000 nm as described above. A bottom part of the concave portion 4MAP shown in FIG. 19 remains as the concave portion 4MP shown in FIG. 20.
In the case in which the silicon oxide is polished by using the CMP method, a silica (SiO2) or ceria (CeO2) based slurry is often used. In respect of productivity, the ceria based slurry having a higher polishing rate is often selected.
Then, a via hole 4HP, a plug 8HP and a wiring 6HP are formed by the same forming method as the method of forming the contact hole 2HP and the like described above. By the above-mentioned steps, the semiconductor device 101P shown in FIG. 17 is obtained. In the case of a multilayer wiring having three layers or more, the above-mentioned steps are repeated predetermined times.
Thereafter, an interlayer insulating film is formed to cover an uppermost wiring, and a silicon nitride film to be a passivation film is formed over the whole surface of the interlayer insulating film by the plasma CVD method or the like. Subsequently, the interlayer insulating film and the like provided on a bonding pad (not shown) are removed by using a photolithographic technique and a dry etching method, thereby exposing the bonding pad.
In the case in which the silicon oxide is polished by using the CMP method as described above, the ceria based slurry having a high polishing rate is often used. At this time, the CMP method using the ceria based slurry includes a polishing step A using the ceria based slurry, a first washing step B of washing the ceria based slurry remaining on a polished surface after the polishing with water and a brush and a second washing step C using (i) a mixed solution of ammonia (NH4OH) and a hydrogen peroxide solution (H2O2) or (ii) dilute hydrofluoric acid (HF). However, the polishing using the ceria based slurry has the following problem.
More specifically, at the polishing step A, the ceria based slurry clogs and remains in the concave portion 4MP (see a slurry residue 50P shown in FIG. 20). Such a slurry residue 50P is scraped out by means of the brush at the first washing step B, and is scattered and coagulates on the interlayer insulating film 4P (see the scattered slurry residue 50P shown in FIG. 21). The scattered slurry residue 50P is scarcely removed with the dilute hydrofluoric acid and cannot fully be removed with the NH4OH/H2O2 mixed solution. For this reason, there has been a problem in that a desirable wiring shape cannot be obtained like a wiring 6P shown in a longitudinal sectional view of FIG. 21 when the wiring is formed on the interlayer insulating film 4P with the slurry residue 50P scattered. Such a disadvantage of the wiring shape causes the wiring to be short-circuited or disconnected, resulting in a reduction in the yield of the semiconductor device and a deterioration in reliability.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining and scattering of a slurry to be used for a CMP method and a method of manufacturing the semiconductor device.
(1) A first aspect of the present invention is directed to a semiconductor device comprising a substrate having a main surface, an interlayer insulating film provided on the main surface of the substrate, at least two underlying layers provided in said interlayer insulating film which are stacked in a direction of a thickness of the interlayer insulating film and are not in contact with each other, and a hole for a mark formed in the interlayer insulating film from a surface of the interlayer insulating film which is opposite to the substrate to the underlying layer which is the closest to the surface of the interlayer insulating film.
(2) A second aspect of the present invention is directed to a semiconductor device comprising a substrate having a main surface, an interlayer insulating film provided on the main surface of the substrate, and a hole for a mark including a plurality of holes each of which is formed in the interlayer insulating film to have an opening entrance on a surface of the interlayer insulating film and each of which has a dimension of less than approximately 1 xcexcm in a plane view of the main surface of the substrate.
(3) A third aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, further comprising a metal layer provided in at least one of the holes.
(4) A fourth aspect of the present invention is directed to the semiconductor device according to the second or third aspect of the present invention, wherein the holes include at least one of a trench-shaped hole and a columnar hole.
(5) A fifth aspect of the present invention is directed to a semiconductor device comprising a substrate having a main surface, an interlayer insulating film provided on the main surface of the substrate, a hole for a mark formed in the interlayer insulating film to have an opening entrance formed on a surface of the interlayer insulating film which is opposite to the substrate, and a metal layer filled in the hole for a mark up to a vicinity of the opening entrance of the hole for a mark.
(6) A sixth aspect of the present invention is directed to a semiconductor device comprising a substrate having a main surface, an interlayer insulating film provided on the main surface of the substrate, a hole for a mark formed in the interlayer insulating film to have an opening entrance formed on a surface of the interlayer insulating film which is opposite to the substrate, and a metal layer provided in the hole for a mark and having a portion of a peak shape which is protruded to narrow the opening entrance.
(7) A seventh aspect of the present invention is directed to a semiconductor device comprising a substrate having a main surface, a first interlayer insulating film provided on the main surface of the substrate, a hole for a mark formed in the first interlayer insulating film to have an opening entrance formed on a surface of the first interlayer insulating film which is opposite to the substrate, a second interlayer insulating film provided to cover the hole for a mark and having a concave portion opened on a surface opposite to the substrate above the hole for a mark, and a dielectric layer provided in the concave portion of the second interlayer insulating film.
(8) An eighth aspect of the present invention is directed to the semiconductor device according to the seventh aspect of the present invention, wherein the concave portion of the second interlayer insulating film is filled with the dielectric layer up to the vicinity of the surface of the second interlayer insulating film.
(9) A ninth aspect of the present invention is directed to the semiconductor device according to the seventh aspect of the present invention, wherein the dielectric layer is provided on at least an inner surface of the concave portion of the second interlayer insulating film.
(10) A tenth aspect of the present invention is directed to the semiconductor device according to any one of the seventh to ninth aspects of the present invention, wherein the dielectric layer is formed of a material to which a slurry to be used for a CMP method sticks with more difficulty than the second interlayer insulating film.
(11) An eleventh aspect of the present invention is directed to the semiconductor device according to any one of the first to tenth aspects of the present invention, wherein the hole for a mark has a dimension of approximately 1 xcexcm or more as seen from above the main surface of the substrate.
(12) A twelfth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) forming a first interlayer insulating film on a main surface of a substrate to have a hole for a mark opened on a surface opposite to the substrate, (b) forming a second interlayer insulating film to cover the hole for a mark, (c) forming a dielectric layer on the second interlayer insulating film, and (d) polishing the second interlayer insulating film by a CMP method after the step (c).
(13) A thirteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the twelfth aspect of the present invention, further comprising the step of (e) removing the dielectric layer remaining after the step (d) is completed.
(14) A fourteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the twelfth or thirteenth aspect of the present invention, wherein the dielectric layer is formed of a material to which a slurry to be used for the CMP method sticks with more difficulty than the second interlayer insulating film.
(15) A fifteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any one of the twelfth to fourteenth aspects of the present invention, wherein the hole for a mark has a dimension of approximately 1 xcexcm or more as seen from above the main surface of the substrate.
(1) According to the first aspect of the present invention, the hole for a mark can be made shallower as compared with the case in which the hole for a mark is provided from the surface of the interlayer insulating film to the main surface of the substrate. Therefore, also in the case in which a further interlayer insulating film is formed to cover the hole for a mark, it is possible to prevent the concave portion from being formed on the further interlayer insulating film above the hole for a mark. Accordingly, it is possible to prevent a slurry from remaining or being scattered by polishing the further interlayer insulating film using a CMP method. As a result, it is possible to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(2) According to the second aspect of the present invention, the hole for a mark includes a plurality of holes having dimensions of less than approximately 1 xcexcm, respectively. Consequently, also in the case in which the further interlayer insulating film is formed to cover the hole for a mark, it is possible to prevent a concave portion from being formed on the further interlayer insulating film above each hole. Accordingly, it is possible to prevent the slurry from remaining or being scattered by polishing the further interlayer insulating film using the CMP method. As a result, it is possible to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(3) According to the third aspect of the present invention, the metal layer is provided in at least one of the holes. Therefore, the formation of the concave portion can be suppressed more reliably. Accordingly, the above-mentioned effect in (2) can be obtained more reliably. In particular, the whole surface side of the interlayer insulating film can be flattened by filling the hole with the metal layer up to the vicinity of the opening entrance thereof and/or providing the metal layer in all the holes. Thus, such an effect can be obtained more remarkably.
In this case, the holes have dimensions of less than approximately 1 xcexcm, respectively. Therefore, the step of forming the metal layer in the holes and the step of filling, with the metal layer (so-called plug), other holes (for example, a contact hole and the like) which are formed in the interlayer insulating film and are smaller than the hole for a mark are carried out at the same time, it is possible to easily fill the holes with the metal layer up to the opening entrances thereof without unnecessarily wasting a time required for the formation.
Furthermore, in other words, the hole for a mark is divided into the holes. Therefore, it is possible to decrease materials forming the metal layer as compared with a large hole for a mark which is not divided. In addition, a time required for forming the metal layer can be shortened. Consequently, it is possible to provide a semiconductor device with a low cost.
(4) According to the fourth aspect of the present invention, in the case in which the holes include at least one of a trench-shaped hole and a columnar hole, the above-mentioned effect in (2) or (3) can be obtained.
(5) According to the fifth aspect of the present invention, the hole for a mark is filled with the metal layer up to the vicinity of the opening entrance thereof. Therefore, the whole surface side of the interlayer insulating film can be flattened. Consequently, also in the case in which a further interlayer insulating film is formed to cover the hole for a mark, it is possible to prevent a concave portion from being formed on the further interlayer insulating film above the hole for a mark. Accordingly, it is possible to prevent the slurry from remaining or being scattered by polishing the further interlayer insulating film using the CMP method. As a result, it is possible to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(6) According to the sixth aspect of the present invention, the opening entrance of the hole for a mark is narrowed by the peak shape of the metal layer. Consequently, also in the case in which a further interlayer insulating film is formed to cover the hole for a mark, it is possible to prevent a concave portion from being formed on the further interlayer insulating film above the hole for a mark. Accordingly, it is possible to prevent the slurry from remaining or being scattered by polishing the further interlayer insulating film using the CMP method. As a result, it is possible to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(7) According to the seventh aspect of the present invention, the dielectric layer is provided in the concave portion of the second interlayer insulating film. Therefore, the concave portion is narrowed corresponding to the dielectric layer as compared with the case in which the dielectric layer is not provided. Accordingly, it is possible to prevent a slurry from remaining or being scattered by polishing the second interlayer insulating film by the CMP method. As a result, it is possible to provide a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(8) According to the eighth aspect of the present invention, the concave portion of the second interlayer insulating film is filled with the dielectric layer up to the vicinity of the surface of the second interlayer insulating film. Accordingly, the above-mentioned effect in (7) can be obtained more reliably.
(9) According to the ninth aspect of the present invention, the dielectric layer is provided on at least the inner surface of the concave portion. Consequently, the concave portion, particularly, the opening entrance of the concave portion is narrowed corresponding to the dielectric layer. Accordingly, the same effect as in the above-mentioned (7) can be obtained.
(10) According to the tenth aspect of the present invention, the dielectric layer is formed of the material to which the slurry to be used for the CMP method sticks with more difficulty than the second interlayer insulating film. Consequently, it is possible to obtain any one of the effects of (7) to (9) more reliably.
(11) According to the eleventh aspect of the present invention, it is possible to obtain any one of the effects of (1) to (10) for the comparatively large hole for a mark which has a dimension of approximately 1 xcexcm or more.
(12) According to the twelfth aspect of the present invention, the second interlayer insulating film is polished by the CMP method after the step (c). Consequently, even if the concave portion is provided on the surface of the second interlayer insulating film, it is possible to fill the concave portion with the dielectric layer and to carry out the above-mentioned polishing. Accordingly, it is possible to prevent a slurry from remaining or being scattered by polishing the second interlayer insulating film using the CMP method. As a result, it is possible to manufacture a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattered slurry.
(13) According to the thirteenth aspect of the present invention, the dielectric layer remaining after the step (d) is removed at the step (e). Therefore, even if the slurry sticks to or remains on the dielectric layer, it is also possible to remove the slurry when removing the dielectric layer. Consequently, the effect of (12) can be obtained more reliably.
(14) According to the fourteenth aspect of the present invention, the dielectric layer is formed of the material to which the slurry to be used for the CMP method sticks with more difficulty than the second interlayer insulating film. Consequently, it is possible to obtain the effect of (12) or (13) more reliably.
(15) According to the fifteenth aspect of the present invention, it is possible to obtain any one of the effects of (12) to (14) for the comparatively large hole for a mark which has a dimension of approximately 1 xcexcm or more.